1. Field of the Invention
The present invention relates to telecommunication network elements and in particular to a port framer in a system platform of such a network element. Furthermore, the present invention relates to a method for carrying out a functional partitioning in a system platform. This application is based on, and claims the benefit of, European Patent Application No. 04290903.6 filed on Apr. 5, 2004, which is incorporated by reference herein.
2. Description of the Prior Art
As it is known, a network element, for instance an ADM (Add/Drop Multiplexer) or a DXC (Digital Cross Connect) comprises one or more input ports, backpanel connections and one or more switching matrices. The ports receive input flows in the form of frames. Presently, the frames could be compliant with SDH, SONET, OTH, ITU-T G.707, G.783, G.709, G.798 Standards. The following description and claims will be referred to SDH Standard only for clarity reasons but this should not be deemed to be a limitation because the scope of the present invention is not limited to SDH.
As far as SDH is concerned, ITU-T G.783 specifies both the components and the methodology that should be used in order to specify SDH functionality of network elements. ITU-T G.783 specifies a library of basic building blocks and a set of rules by which they may be combined in order to describe a digital transmission equipment. The library comprises the functional building blocks needed to specify completely the generic functional structure of the Synchronous Digital Hierarchy. In order to be compliant with this Recommendation, equipment must be composed as an interconnection of a subset of these functional blocks contained within the Recommendation. The interconnections of these blocks should obey the combination rules given. The specification method is based on functional decomposition of the equipment into atomic, and compound functions. The description is generic and no particular physical partitioning of functions is implied.
Fundamentally, ITU-T G.798 specifies both the components and the methodology that should be used in order to specify OTH functionality of network elements.
The prior art devices for processing frames, with each frame comprising overhead and payload, comprise a single hardware module. The single hardware module processes both the payload and overhead by carrying out adaptation, termination and cross-connection functions. The hardware module according to the prior art is generally composed of an application-specific integrated circuit, ASIC, straightforward implementing the functional partitioning described by the above mentioned standards.
Advantageously, straight and literal implementation of Standards functional partitioning into a full ASIC system provides high integration features and high performances. Disadvantageously, ASIC devices do not provide flexibility on Standard evolution and on system requirements. In other words, when a reference Standard becomes changed or there is the need to change the system requirements, an ASIC device is unable to follow such changes.
Providing the whole Standard functional partitioning features into an ASIC device results in a highly risky implementation due to the ASIC slow turnaround for silicon respin delay , which comprises full layout and fab activities and high NRE (Non-Recurring-Engineering) cost, which mostly includes the mask cost. It is known that an ASIC device is not flexible in providing support to different Standards in the same device area with the same cost; on the contrary, different Standards supported in the same ASIC require more silicon area and raises costs for all applications. Furthermore, an application-specific integrated circuit does not match fastest time-to-market requirement due to slow and complex verification (based on simulation) of a full-featured ASIC. This results in a later ASIC availability for system integration.